1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a lateral semiconductor device (lateral transistor) having a low on-resistance and a high withstand voltage.
2. Description of the Background Art
Conventionally, various MOS transistors (lateral semiconductor devices), which have a further reduced level of on-resistance while maintaining a high withstand voltage, have been proposed. For example, Japanese Laid-Open Patent Publication No. 2002-43562 discloses an example of a conventional MOS transistor.
FIG. 8 is a cross-sectional view of an example of a conventional MOS transistor 800 (hereinafter referred to as a semiconductor device 800). The semiconductor device 800 comprises a P-type semiconductor substrate 810, a source electrode 807, a drain electrode 805, agate insulating film 814, a gate electrode 809, and an insulating film 812. In the P-type semiconductor substrate 810, an N-type extended drain region 802, an N-type high-concentration drain region 803, P-type buried regions 804a and 804b, an antipunch through region 808, an N-type source region 801, and a P-type substrate contact region 806 are formed.
In the P-type semiconductor substrate 810, the N-type source region 801 and the P-type substrate contact region 806 are formed adjacent to each other. Upper surfaces of the N-type source region 801 and the P-type substrate contact region 806 are in contact with an lower surface of the source electrode 807 in the vicinity of a boundary between the N-type source region 801 and the P-type substrate contact region 806. The antipunch through region 808 has a higher P-type impurity concentration than that of the P-type semiconductor substrate 810, and is formed surrounding the N-type source region 801 and the P-type substrate contact region 806.
The N-type high-concentration drain region 803 is formed in the extended drain region 802. An upper surface of the N-type high-concentration drain region 803 is connected to a lower surface of the drain electrode 805. The N-type high-concentration drain region 803 has a higher N-type impurity concentration than that of the extended drain region 802. A region of an upper surface of the P-type semiconductor substrate 810, on which the source electrode 807 and the drain electrode 805 are not formed, is covered with the gate insulating film 814 and the insulating film 812.
The gate electrode 809 is formed over a region of the P-type semiconductor substrate 810 between the extended drain region 802 and the antipunch through region 808 via the gate insulating film 814. When a predetermined amount of voltage is applied to the gate electrode 809, a channel region 811 appears at the surface of the semiconductor substrate 810 between the antipunch through region 808 and the extended drain region 802.
The P-type buried regions 804a and 804b formed in the extended drain region 802 are connected to the P-type semiconductor substrate 810 in a cross section which is not shown in FIG. 8. Therefore, the P-type buried regions 804a and 804b have the same reference potential as that of the P-type semiconductor substrate 810.
When a high voltage is applied to the drain electrode 805 and the predetermined amount of gate voltage is not applied to the gate electrode 809 (off time), the P-type semiconductor substrate 810 and the extended drain region 802 are reversely biased, and the P-type buried region 804a and 804b and the extended drain region 802 are reversely biased. A depletion layer occurs at a boundary between these regions. The occurrence of such a depletion layer during the off time enables the semiconductor device 800 to withstand a high voltage.
When a high voltage is applied to the drain electrode 805 and the predetermined gate voltage is applied to the gate electrode 809 (on-time), a current flows from the drain electrode 805 via the N-type high-concentration drain region 803, the extended drain region 802, the channel region 811, the antipunch through region 808 and the N-type source region 801 to the source electrode 807. In the extended drain region 802, as indicated with a dashed line arrow in FIG. 8, currents flow over the P-type buried region 804a, between the P-type buried regions 804a and 804b, and below the P-type buried region 804b. 
The resistance value of the extended drain region 802 can be represented by the combined resistance of a parallel connection of current paths located over the P-type buried region 804a, between the P-type buried regions 804a and 804b, and below the P-type buried region 804b. As the N-type impurity concentration of the extended drain region 802 is increased, the resistance value of the extended drain region 802 is decreased, leading to a decrease in on-resistance between the source electrode 807 and the drain electrode 805.
As described above, larger depletion layers occur when the P-type buried regions 804a and 804b are provided than when the P-type buried regions 804a and 804b are not provided. Therefore, in the semiconductor device 800, a withstand voltage can be maintained high at a higher N-type impurity concentration of the extended drain region 802 than when the P-type buried regions 804a and 804b are not formed. Therefore, in the semiconductor device 800, the on-resistance can be reduced as compared to semiconductor devices without any P-type buried region.
However, the degree of the low on-resistance of the conventional semiconductor device 800 is limited due to the following reasons. The extended drain region 802 is formed by implantation and thermal diffusion of N-type impurity ions from a surface of the P-type semiconductor substrate 810. Therefore, the N-type impurity concentration of the extended drain region 802 may be a desired concentration in the vicinity of the surface thereof but decreases with an increase in depth. Therefore, the on-resistance of an actually manufactured semiconductor device is high compared to an ideal semiconductor device, in which the entire extended drain region 802 has a uniform N-type impurity concentration which is equal to an N-type impurity concentration at an upper portion thereof. When the N-type impurity concentration is increased in the entire extended drain region 802 by increasing the amount of implanted N-type impurity in order to reduce the on-resistance, the width of a depletion layer occurring during the off time is narrowed, so that a high withstand voltage cannot be maintained. Therefore, in the semiconductor device 800, the N-type impurity concentration can be increased only up to an extent which can maintain a withstand voltage, so that the degree of the low on-resistance is limited.